;
; File Name: cyfitteriar.inc
; 
; PSoC Creator  4.1 Update 1
;
; Description:
; 
;
;-------------------------------------------------------------------------------
; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
; You may use this file only in accordance with the license, terms, conditions, 
; disclaimers, and limitations in the end user license agreement accompanying 
; the software package with which this file was provided.
;-------------------------------------------------------------------------------

#ifndef INCLUDED_CYFITTERIAR_INC
#define INCLUDED_CYFITTERIAR_INC
    INCLUDE cydeviceiar.inc
    INCLUDE cydeviceiar_trm.inc

/* ADC_DMA */
ADC_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL2
ADC_DMA__DRQ_NUMBER EQU 10
ADC_DMA__NUMBEROF_TDS EQU 0
ADC_DMA__PRIORITY EQU 2
ADC_DMA__TERMIN_EN EQU 0
ADC_DMA__TERMIN_SEL EQU 0
ADC_DMA__TERMOUT0_EN EQU 1
ADC_DMA__TERMOUT0_SEL EQU 10
ADC_DMA__TERMOUT1_EN EQU 0
ADC_DMA__TERMOUT1_SEL EQU 0

/* BT_GPIO3 */
BT_GPIO3__0__INTTYPE EQU CYREG_PICU5_INTTYPE0
BT_GPIO3__0__MASK EQU 0x01
BT_GPIO3__0__PC EQU CYREG_PRT5_PC0
BT_GPIO3__0__PORT EQU 5
BT_GPIO3__0__SHIFT EQU 0
BT_GPIO3__AG EQU CYREG_PRT5_AG
BT_GPIO3__AMUX EQU CYREG_PRT5_AMUX
BT_GPIO3__BIE EQU CYREG_PRT5_BIE
BT_GPIO3__BIT_MASK EQU CYREG_PRT5_BIT_MASK
BT_GPIO3__BYP EQU CYREG_PRT5_BYP
BT_GPIO3__CTL EQU CYREG_PRT5_CTL
BT_GPIO3__DM0 EQU CYREG_PRT5_DM0
BT_GPIO3__DM1 EQU CYREG_PRT5_DM1
BT_GPIO3__DM2 EQU CYREG_PRT5_DM2
BT_GPIO3__DR EQU CYREG_PRT5_DR
BT_GPIO3__INP_DIS EQU CYREG_PRT5_INP_DIS
BT_GPIO3__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU5_BASE
BT_GPIO3__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
BT_GPIO3__LCD_EN EQU CYREG_PRT5_LCD_EN
BT_GPIO3__MASK EQU 0x01
BT_GPIO3__PORT EQU 5
BT_GPIO3__PRT EQU CYREG_PRT5_PRT
BT_GPIO3__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
BT_GPIO3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
BT_GPIO3__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
BT_GPIO3__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
BT_GPIO3__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
BT_GPIO3__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
BT_GPIO3__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
BT_GPIO3__PS EQU CYREG_PRT5_PS
BT_GPIO3__SHIFT EQU 0
BT_GPIO3__SLW EQU CYREG_PRT5_SLW

/* BT_GPIO4 */
BT_GPIO4__0__INTTYPE EQU CYREG_PICU5_INTTYPE1
BT_GPIO4__0__MASK EQU 0x02
BT_GPIO4__0__PC EQU CYREG_PRT5_PC1
BT_GPIO4__0__PORT EQU 5
BT_GPIO4__0__SHIFT EQU 1
BT_GPIO4__AG EQU CYREG_PRT5_AG
BT_GPIO4__AMUX EQU CYREG_PRT5_AMUX
BT_GPIO4__BIE EQU CYREG_PRT5_BIE
BT_GPIO4__BIT_MASK EQU CYREG_PRT5_BIT_MASK
BT_GPIO4__BYP EQU CYREG_PRT5_BYP
BT_GPIO4__CTL EQU CYREG_PRT5_CTL
BT_GPIO4__DM0 EQU CYREG_PRT5_DM0
BT_GPIO4__DM1 EQU CYREG_PRT5_DM1
BT_GPIO4__DM2 EQU CYREG_PRT5_DM2
BT_GPIO4__DR EQU CYREG_PRT5_DR
BT_GPIO4__INP_DIS EQU CYREG_PRT5_INP_DIS
BT_GPIO4__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU5_BASE
BT_GPIO4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
BT_GPIO4__LCD_EN EQU CYREG_PRT5_LCD_EN
BT_GPIO4__MASK EQU 0x02
BT_GPIO4__PORT EQU 5
BT_GPIO4__PRT EQU CYREG_PRT5_PRT
BT_GPIO4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
BT_GPIO4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
BT_GPIO4__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
BT_GPIO4__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
BT_GPIO4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
BT_GPIO4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
BT_GPIO4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
BT_GPIO4__PS EQU CYREG_PRT5_PS
BT_GPIO4__SHIFT EQU 1
BT_GPIO4__SLW EQU CYREG_PRT5_SLW

/* BT_GPIO6 */
BT_GPIO6__0__INTTYPE EQU CYREG_PICU5_INTTYPE2
BT_GPIO6__0__MASK EQU 0x04
BT_GPIO6__0__PC EQU CYREG_PRT5_PC2
BT_GPIO6__0__PORT EQU 5
BT_GPIO6__0__SHIFT EQU 2
BT_GPIO6__AG EQU CYREG_PRT5_AG
BT_GPIO6__AMUX EQU CYREG_PRT5_AMUX
BT_GPIO6__BIE EQU CYREG_PRT5_BIE
BT_GPIO6__BIT_MASK EQU CYREG_PRT5_BIT_MASK
BT_GPIO6__BYP EQU CYREG_PRT5_BYP
BT_GPIO6__CTL EQU CYREG_PRT5_CTL
BT_GPIO6__DM0 EQU CYREG_PRT5_DM0
BT_GPIO6__DM1 EQU CYREG_PRT5_DM1
BT_GPIO6__DM2 EQU CYREG_PRT5_DM2
BT_GPIO6__DR EQU CYREG_PRT5_DR
BT_GPIO6__INP_DIS EQU CYREG_PRT5_INP_DIS
BT_GPIO6__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU5_BASE
BT_GPIO6__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
BT_GPIO6__LCD_EN EQU CYREG_PRT5_LCD_EN
BT_GPIO6__MASK EQU 0x04
BT_GPIO6__PORT EQU 5
BT_GPIO6__PRT EQU CYREG_PRT5_PRT
BT_GPIO6__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
BT_GPIO6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
BT_GPIO6__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
BT_GPIO6__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
BT_GPIO6__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
BT_GPIO6__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
BT_GPIO6__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
BT_GPIO6__PS EQU CYREG_PRT5_PS
BT_GPIO6__SHIFT EQU 2
BT_GPIO6__SLW EQU CYREG_PRT5_SLW

/* BT_GPIO7 */
BT_GPIO7__0__INTTYPE EQU CYREG_PICU5_INTTYPE3
BT_GPIO7__0__MASK EQU 0x08
BT_GPIO7__0__PC EQU CYREG_PRT5_PC3
BT_GPIO7__0__PORT EQU 5
BT_GPIO7__0__SHIFT EQU 3
BT_GPIO7__AG EQU CYREG_PRT5_AG
BT_GPIO7__AMUX EQU CYREG_PRT5_AMUX
BT_GPIO7__BIE EQU CYREG_PRT5_BIE
BT_GPIO7__BIT_MASK EQU CYREG_PRT5_BIT_MASK
BT_GPIO7__BYP EQU CYREG_PRT5_BYP
BT_GPIO7__CTL EQU CYREG_PRT5_CTL
BT_GPIO7__DM0 EQU CYREG_PRT5_DM0
BT_GPIO7__DM1 EQU CYREG_PRT5_DM1
BT_GPIO7__DM2 EQU CYREG_PRT5_DM2
BT_GPIO7__DR EQU CYREG_PRT5_DR
BT_GPIO7__INP_DIS EQU CYREG_PRT5_INP_DIS
BT_GPIO7__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU5_BASE
BT_GPIO7__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
BT_GPIO7__LCD_EN EQU CYREG_PRT5_LCD_EN
BT_GPIO7__MASK EQU 0x08
BT_GPIO7__PORT EQU 5
BT_GPIO7__PRT EQU CYREG_PRT5_PRT
BT_GPIO7__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
BT_GPIO7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
BT_GPIO7__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
BT_GPIO7__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
BT_GPIO7__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
BT_GPIO7__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
BT_GPIO7__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
BT_GPIO7__PS EQU CYREG_PRT5_PS
BT_GPIO7__SHIFT EQU 3
BT_GPIO7__SLW EQU CYREG_PRT5_SLW

/* BT_RECEIVE_ISR */
BT_RECEIVE_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
BT_RECEIVE_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
BT_RECEIVE_ISR__INTC_MASK EQU 0x01
BT_RECEIVE_ISR__INTC_NUMBER EQU 0
BT_RECEIVE_ISR__INTC_PRIOR_NUM EQU 7
BT_RECEIVE_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
BT_RECEIVE_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
BT_RECEIVE_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

/* BT_RESETn */
BT_RESETn__0__INTTYPE EQU CYREG_PICU1_INTTYPE7
BT_RESETn__0__MASK EQU 0x80
BT_RESETn__0__PC EQU CYREG_PRT1_PC7
BT_RESETn__0__PORT EQU 1
BT_RESETn__0__SHIFT EQU 7
BT_RESETn__AG EQU CYREG_PRT1_AG
BT_RESETn__AMUX EQU CYREG_PRT1_AMUX
BT_RESETn__BIE EQU CYREG_PRT1_BIE
BT_RESETn__BIT_MASK EQU CYREG_PRT1_BIT_MASK
BT_RESETn__BYP EQU CYREG_PRT1_BYP
BT_RESETn__CTL EQU CYREG_PRT1_CTL
BT_RESETn__DM0 EQU CYREG_PRT1_DM0
BT_RESETn__DM1 EQU CYREG_PRT1_DM1
BT_RESETn__DM2 EQU CYREG_PRT1_DM2
BT_RESETn__DR EQU CYREG_PRT1_DR
BT_RESETn__INP_DIS EQU CYREG_PRT1_INP_DIS
BT_RESETn__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU1_BASE
BT_RESETn__LCD_COM_SEG EQU CYREG_PRT1_LCD_COM_SEG
BT_RESETn__LCD_EN EQU CYREG_PRT1_LCD_EN
BT_RESETn__MASK EQU 0x80
BT_RESETn__PORT EQU 1
BT_RESETn__PRT EQU CYREG_PRT1_PRT
BT_RESETn__PRTDSI__CAPS_SEL EQU CYREG_PRT1_CAPS_SEL
BT_RESETn__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT1_DBL_SYNC_IN
BT_RESETn__PRTDSI__OE_SEL0 EQU CYREG_PRT1_OE_SEL0
BT_RESETn__PRTDSI__OE_SEL1 EQU CYREG_PRT1_OE_SEL1
BT_RESETn__PRTDSI__OUT_SEL0 EQU CYREG_PRT1_OUT_SEL0
BT_RESETn__PRTDSI__OUT_SEL1 EQU CYREG_PRT1_OUT_SEL1
BT_RESETn__PRTDSI__SYNC_OUT EQU CYREG_PRT1_SYNC_OUT
BT_RESETn__PS EQU CYREG_PRT1_PS
BT_RESETn__SHIFT EQU 7
BT_RESETn__SLW EQU CYREG_PRT1_SLW

/* BT_UART_BUART */
BT_UART_BUART_sRX_RxBitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
BT_UART_BUART_sRX_RxBitCounter__CONTROL_REG EQU CYREG_B0_UDB15_CTL
BT_UART_BUART_sRX_RxBitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
BT_UART_BUART_sRX_RxBitCounter__COUNT_REG EQU CYREG_B0_UDB15_CTL
BT_UART_BUART_sRX_RxBitCounter__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
BT_UART_BUART_sRX_RxBitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
BT_UART_BUART_sRX_RxBitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
BT_UART_BUART_sRX_RxBitCounter__PERIOD_REG EQU CYREG_B0_UDB15_MSK
BT_UART_BUART_sRX_RxBitCounter_ST__MASK_REG EQU CYREG_B0_UDB15_MSK
BT_UART_BUART_sRX_RxBitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
BT_UART_BUART_sRX_RxBitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
BT_UART_BUART_sRX_RxBitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
BT_UART_BUART_sRX_RxBitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL
BT_UART_BUART_sRX_RxBitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL
BT_UART_BUART_sRX_RxBitCounter_ST__STATUS_REG EQU CYREG_B0_UDB15_ST
BT_UART_BUART_sRX_RxShifter_u0__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0
BT_UART_BUART_sRX_RxShifter_u0__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1
BT_UART_BUART_sRX_RxShifter_u0__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0
BT_UART_BUART_sRX_RxShifter_u0__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1
BT_UART_BUART_sRX_RxShifter_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
BT_UART_BUART_sRX_RxShifter_u0__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0
BT_UART_BUART_sRX_RxShifter_u0__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1
BT_UART_BUART_sRX_RxShifter_u0__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1
BT_UART_BUART_sRX_RxShifter_u0__A0_REG EQU CYREG_B0_UDB12_A0
BT_UART_BUART_sRX_RxShifter_u0__A1_REG EQU CYREG_B0_UDB12_A1
BT_UART_BUART_sRX_RxShifter_u0__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1
BT_UART_BUART_sRX_RxShifter_u0__D0_REG EQU CYREG_B0_UDB12_D0
BT_UART_BUART_sRX_RxShifter_u0__D1_REG EQU CYREG_B0_UDB12_D1
BT_UART_BUART_sRX_RxShifter_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
BT_UART_BUART_sRX_RxShifter_u0__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1
BT_UART_BUART_sRX_RxShifter_u0__F0_REG EQU CYREG_B0_UDB12_F0
BT_UART_BUART_sRX_RxShifter_u0__F1_REG EQU CYREG_B0_UDB12_F1
BT_UART_BUART_sRX_RxSts__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
BT_UART_BUART_sRX_RxSts__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
BT_UART_BUART_sRX_RxSts__3__MASK EQU 0x08
BT_UART_BUART_sRX_RxSts__3__POS EQU 3
BT_UART_BUART_sRX_RxSts__4__MASK EQU 0x10
BT_UART_BUART_sRX_RxSts__4__POS EQU 4
BT_UART_BUART_sRX_RxSts__5__MASK EQU 0x20
BT_UART_BUART_sRX_RxSts__5__POS EQU 5
BT_UART_BUART_sRX_RxSts__MASK EQU 0x38
BT_UART_BUART_sRX_RxSts__MASK_REG EQU CYREG_B0_UDB00_MSK
BT_UART_BUART_sRX_RxSts__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
BT_UART_BUART_sRX_RxSts__STATUS_REG EQU CYREG_B0_UDB00_ST
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG EQU CYREG_B0_UDB10_11_A0
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG EQU CYREG_B0_UDB10_11_A1
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG EQU CYREG_B0_UDB10_11_D0
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG EQU CYREG_B0_UDB10_11_D1
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG EQU CYREG_B0_UDB10_11_F0
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG EQU CYREG_B0_UDB10_11_F1
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG EQU CYREG_B0_UDB10_A0_A1
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG EQU CYREG_B0_UDB10_A0
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG EQU CYREG_B0_UDB10_A1
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG EQU CYREG_B0_UDB10_D0_D1
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG EQU CYREG_B0_UDB10_D0
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG EQU CYREG_B0_UDB10_D1
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG EQU CYREG_B0_UDB10_F0_F1
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG EQU CYREG_B0_UDB10_F0
BT_UART_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG EQU CYREG_B0_UDB10_F1
BT_UART_BUART_sTX_TxShifter_u0__16BIT_A0_REG EQU CYREG_B0_UDB14_15_A0
BT_UART_BUART_sTX_TxShifter_u0__16BIT_A1_REG EQU CYREG_B0_UDB14_15_A1
BT_UART_BUART_sTX_TxShifter_u0__16BIT_D0_REG EQU CYREG_B0_UDB14_15_D0
BT_UART_BUART_sTX_TxShifter_u0__16BIT_D1_REG EQU CYREG_B0_UDB14_15_D1
BT_UART_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
BT_UART_BUART_sTX_TxShifter_u0__16BIT_F0_REG EQU CYREG_B0_UDB14_15_F0
BT_UART_BUART_sTX_TxShifter_u0__16BIT_F1_REG EQU CYREG_B0_UDB14_15_F1
BT_UART_BUART_sTX_TxShifter_u0__A0_A1_REG EQU CYREG_B0_UDB14_A0_A1
BT_UART_BUART_sTX_TxShifter_u0__A0_REG EQU CYREG_B0_UDB14_A0
BT_UART_BUART_sTX_TxShifter_u0__A1_REG EQU CYREG_B0_UDB14_A1
BT_UART_BUART_sTX_TxShifter_u0__D0_D1_REG EQU CYREG_B0_UDB14_D0_D1
BT_UART_BUART_sTX_TxShifter_u0__D0_REG EQU CYREG_B0_UDB14_D0
BT_UART_BUART_sTX_TxShifter_u0__D1_REG EQU CYREG_B0_UDB14_D1
BT_UART_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
BT_UART_BUART_sTX_TxShifter_u0__F0_F1_REG EQU CYREG_B0_UDB14_F0_F1
BT_UART_BUART_sTX_TxShifter_u0__F0_REG EQU CYREG_B0_UDB14_F0
BT_UART_BUART_sTX_TxShifter_u0__F1_REG EQU CYREG_B0_UDB14_F1
BT_UART_BUART_sTX_TxSts__0__MASK EQU 0x01
BT_UART_BUART_sTX_TxSts__0__POS EQU 0
BT_UART_BUART_sTX_TxSts__1__MASK EQU 0x02
BT_UART_BUART_sTX_TxSts__1__POS EQU 1
BT_UART_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
BT_UART_BUART_sTX_TxSts__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
BT_UART_BUART_sTX_TxSts__2__MASK EQU 0x04
BT_UART_BUART_sTX_TxSts__2__POS EQU 2
BT_UART_BUART_sTX_TxSts__3__MASK EQU 0x08
BT_UART_BUART_sTX_TxSts__3__POS EQU 3
BT_UART_BUART_sTX_TxSts__MASK EQU 0x0F
BT_UART_BUART_sTX_TxSts__MASK_REG EQU CYREG_B0_UDB13_MSK
BT_UART_BUART_sTX_TxSts__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
BT_UART_BUART_sTX_TxSts__STATUS_REG EQU CYREG_B0_UDB13_ST

/* BT_UART_CTS */
BT_UART_CTS__0__INTTYPE EQU CYREG_PICU6_INTTYPE7
BT_UART_CTS__0__MASK EQU 0x80
BT_UART_CTS__0__PC EQU CYREG_PRT6_PC7
BT_UART_CTS__0__PORT EQU 6
BT_UART_CTS__0__SHIFT EQU 7
BT_UART_CTS__AG EQU CYREG_PRT6_AG
BT_UART_CTS__AMUX EQU CYREG_PRT6_AMUX
BT_UART_CTS__BIE EQU CYREG_PRT6_BIE
BT_UART_CTS__BIT_MASK EQU CYREG_PRT6_BIT_MASK
BT_UART_CTS__BYP EQU CYREG_PRT6_BYP
BT_UART_CTS__CTL EQU CYREG_PRT6_CTL
BT_UART_CTS__DM0 EQU CYREG_PRT6_DM0
BT_UART_CTS__DM1 EQU CYREG_PRT6_DM1
BT_UART_CTS__DM2 EQU CYREG_PRT6_DM2
BT_UART_CTS__DR EQU CYREG_PRT6_DR
BT_UART_CTS__INP_DIS EQU CYREG_PRT6_INP_DIS
BT_UART_CTS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
BT_UART_CTS__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
BT_UART_CTS__LCD_EN EQU CYREG_PRT6_LCD_EN
BT_UART_CTS__MASK EQU 0x80
BT_UART_CTS__PORT EQU 6
BT_UART_CTS__PRT EQU CYREG_PRT6_PRT
BT_UART_CTS__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
BT_UART_CTS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
BT_UART_CTS__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
BT_UART_CTS__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
BT_UART_CTS__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
BT_UART_CTS__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
BT_UART_CTS__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
BT_UART_CTS__PS EQU CYREG_PRT6_PS
BT_UART_CTS__SHIFT EQU 7
BT_UART_CTS__SLW EQU CYREG_PRT6_SLW

/* BT_UART_IntClock */
BT_UART_IntClock__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
BT_UART_IntClock__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
BT_UART_IntClock__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
BT_UART_IntClock__CFG2_SRC_SEL_MASK EQU 0x07
BT_UART_IntClock__INDEX EQU 0x01
BT_UART_IntClock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
BT_UART_IntClock__PM_ACT_MSK EQU 0x02
BT_UART_IntClock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
BT_UART_IntClock__PM_STBY_MSK EQU 0x02

/* BT_UART_RTS */
BT_UART_RTS__0__INTTYPE EQU CYREG_PICU6_INTTYPE6
BT_UART_RTS__0__MASK EQU 0x40
BT_UART_RTS__0__PC EQU CYREG_PRT6_PC6
BT_UART_RTS__0__PORT EQU 6
BT_UART_RTS__0__SHIFT EQU 6
BT_UART_RTS__AG EQU CYREG_PRT6_AG
BT_UART_RTS__AMUX EQU CYREG_PRT6_AMUX
BT_UART_RTS__BIE EQU CYREG_PRT6_BIE
BT_UART_RTS__BIT_MASK EQU CYREG_PRT6_BIT_MASK
BT_UART_RTS__BYP EQU CYREG_PRT6_BYP
BT_UART_RTS__CTL EQU CYREG_PRT6_CTL
BT_UART_RTS__DM0 EQU CYREG_PRT6_DM0
BT_UART_RTS__DM1 EQU CYREG_PRT6_DM1
BT_UART_RTS__DM2 EQU CYREG_PRT6_DM2
BT_UART_RTS__DR EQU CYREG_PRT6_DR
BT_UART_RTS__INP_DIS EQU CYREG_PRT6_INP_DIS
BT_UART_RTS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
BT_UART_RTS__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
BT_UART_RTS__LCD_EN EQU CYREG_PRT6_LCD_EN
BT_UART_RTS__MASK EQU 0x40
BT_UART_RTS__PORT EQU 6
BT_UART_RTS__PRT EQU CYREG_PRT6_PRT
BT_UART_RTS__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
BT_UART_RTS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
BT_UART_RTS__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
BT_UART_RTS__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
BT_UART_RTS__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
BT_UART_RTS__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
BT_UART_RTS__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
BT_UART_RTS__PS EQU CYREG_PRT6_PS
BT_UART_RTS__SHIFT EQU 6
BT_UART_RTS__SLW EQU CYREG_PRT6_SLW

/* BT_UART_RX */
BT_UART_RX__0__INTTYPE EQU CYREG_PICU6_INTTYPE4
BT_UART_RX__0__MASK EQU 0x10
BT_UART_RX__0__PC EQU CYREG_PRT6_PC4
BT_UART_RX__0__PORT EQU 6
BT_UART_RX__0__SHIFT EQU 4
BT_UART_RX__AG EQU CYREG_PRT6_AG
BT_UART_RX__AMUX EQU CYREG_PRT6_AMUX
BT_UART_RX__BIE EQU CYREG_PRT6_BIE
BT_UART_RX__BIT_MASK EQU CYREG_PRT6_BIT_MASK
BT_UART_RX__BYP EQU CYREG_PRT6_BYP
BT_UART_RX__CTL EQU CYREG_PRT6_CTL
BT_UART_RX__DM0 EQU CYREG_PRT6_DM0
BT_UART_RX__DM1 EQU CYREG_PRT6_DM1
BT_UART_RX__DM2 EQU CYREG_PRT6_DM2
BT_UART_RX__DR EQU CYREG_PRT6_DR
BT_UART_RX__INP_DIS EQU CYREG_PRT6_INP_DIS
BT_UART_RX__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
BT_UART_RX__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
BT_UART_RX__LCD_EN EQU CYREG_PRT6_LCD_EN
BT_UART_RX__MASK EQU 0x10
BT_UART_RX__PORT EQU 6
BT_UART_RX__PRT EQU CYREG_PRT6_PRT
BT_UART_RX__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
BT_UART_RX__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
BT_UART_RX__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
BT_UART_RX__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
BT_UART_RX__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
BT_UART_RX__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
BT_UART_RX__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
BT_UART_RX__PS EQU CYREG_PRT6_PS
BT_UART_RX__SHIFT EQU 4
BT_UART_RX__SLW EQU CYREG_PRT6_SLW

/* BT_UART_TX */
BT_UART_TX__0__INTTYPE EQU CYREG_PICU6_INTTYPE5
BT_UART_TX__0__MASK EQU 0x20
BT_UART_TX__0__PC EQU CYREG_PRT6_PC5
BT_UART_TX__0__PORT EQU 6
BT_UART_TX__0__SHIFT EQU 5
BT_UART_TX__AG EQU CYREG_PRT6_AG
BT_UART_TX__AMUX EQU CYREG_PRT6_AMUX
BT_UART_TX__BIE EQU CYREG_PRT6_BIE
BT_UART_TX__BIT_MASK EQU CYREG_PRT6_BIT_MASK
BT_UART_TX__BYP EQU CYREG_PRT6_BYP
BT_UART_TX__CTL EQU CYREG_PRT6_CTL
BT_UART_TX__DM0 EQU CYREG_PRT6_DM0
BT_UART_TX__DM1 EQU CYREG_PRT6_DM1
BT_UART_TX__DM2 EQU CYREG_PRT6_DM2
BT_UART_TX__DR EQU CYREG_PRT6_DR
BT_UART_TX__INP_DIS EQU CYREG_PRT6_INP_DIS
BT_UART_TX__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
BT_UART_TX__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
BT_UART_TX__LCD_EN EQU CYREG_PRT6_LCD_EN
BT_UART_TX__MASK EQU 0x20
BT_UART_TX__PORT EQU 6
BT_UART_TX__PRT EQU CYREG_PRT6_PRT
BT_UART_TX__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
BT_UART_TX__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
BT_UART_TX__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
BT_UART_TX__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
BT_UART_TX__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
BT_UART_TX__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
BT_UART_TX__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
BT_UART_TX__PS EQU CYREG_PRT6_PS
BT_UART_TX__SHIFT EQU 5
BT_UART_TX__SLW EQU CYREG_PRT6_SLW

/* ECG_ADC */
ECG_ADC_DEC__COHER EQU CYREG_DEC_COHER
ECG_ADC_DEC__CR EQU CYREG_DEC_CR
ECG_ADC_DEC__DR1 EQU CYREG_DEC_DR1
ECG_ADC_DEC__DR2 EQU CYREG_DEC_DR2
ECG_ADC_DEC__DR2H EQU CYREG_DEC_DR2H
ECG_ADC_DEC__GCOR EQU CYREG_DEC_GCOR
ECG_ADC_DEC__GCORH EQU CYREG_DEC_GCORH
ECG_ADC_DEC__GVAL EQU CYREG_DEC_GVAL
ECG_ADC_DEC__OCOR EQU CYREG_DEC_OCOR
ECG_ADC_DEC__OCORH EQU CYREG_DEC_OCORH
ECG_ADC_DEC__OCORM EQU CYREG_DEC_OCORM
ECG_ADC_DEC__OUTSAMP EQU CYREG_DEC_OUTSAMP
ECG_ADC_DEC__OUTSAMPH EQU CYREG_DEC_OUTSAMPH
ECG_ADC_DEC__OUTSAMPM EQU CYREG_DEC_OUTSAMPM
ECG_ADC_DEC__OUTSAMPS EQU CYREG_DEC_OUTSAMPS
ECG_ADC_DEC__PM_ACT_CFG EQU CYREG_PM_ACT_CFG10
ECG_ADC_DEC__PM_ACT_MSK EQU 0x01
ECG_ADC_DEC__PM_STBY_CFG EQU CYREG_PM_STBY_CFG10
ECG_ADC_DEC__PM_STBY_MSK EQU 0x01
ECG_ADC_DEC__SHIFT1 EQU CYREG_DEC_SHIFT1
ECG_ADC_DEC__SHIFT2 EQU CYREG_DEC_SHIFT2
ECG_ADC_DEC__SR EQU CYREG_DEC_SR
ECG_ADC_DEC__TRIM__M1 EQU CYREG_FLSHID_CUST_TABLES_DEC_M1
ECG_ADC_DEC__TRIM__M2 EQU CYREG_FLSHID_CUST_TABLES_DEC_M2
ECG_ADC_DEC__TRIM__M3 EQU CYREG_FLSHID_CUST_TABLES_DEC_M3
ECG_ADC_DEC__TRIM__M4 EQU CYREG_FLSHID_CUST_TABLES_DEC_M4
ECG_ADC_DEC__TRIM__M5 EQU CYREG_FLSHID_CUST_TABLES_DEC_M5
ECG_ADC_DEC__TRIM__M6 EQU CYREG_FLSHID_CUST_TABLES_DEC_M6
ECG_ADC_DEC__TRIM__M7 EQU CYREG_FLSHID_CUST_TABLES_DEC_M7
ECG_ADC_DEC__TRIM__M8 EQU CYREG_FLSHID_CUST_TABLES_DEC_M8
ECG_ADC_Delay_Timer_TimerUDB_rstSts_stsreg__0__MASK EQU 0x01
ECG_ADC_Delay_Timer_TimerUDB_rstSts_stsreg__0__POS EQU 0
ECG_ADC_Delay_Timer_TimerUDB_rstSts_stsreg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
ECG_ADC_Delay_Timer_TimerUDB_rstSts_stsreg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
ECG_ADC_Delay_Timer_TimerUDB_rstSts_stsreg__2__MASK EQU 0x04
ECG_ADC_Delay_Timer_TimerUDB_rstSts_stsreg__2__POS EQU 2
ECG_ADC_Delay_Timer_TimerUDB_rstSts_stsreg__3__MASK EQU 0x08
ECG_ADC_Delay_Timer_TimerUDB_rstSts_stsreg__3__POS EQU 3
ECG_ADC_Delay_Timer_TimerUDB_rstSts_stsreg__MASK EQU 0x0D
ECG_ADC_Delay_Timer_TimerUDB_rstSts_stsreg__MASK_REG EQU CYREG_B0_UDB11_MSK
ECG_ADC_Delay_Timer_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
ECG_ADC_Delay_Timer_TimerUDB_rstSts_stsreg__STATUS_REG EQU CYREG_B0_UDB11_ST
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__A0_REG EQU CYREG_B0_UDB11_A0
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__A1_REG EQU CYREG_B0_UDB11_A1
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__D0_REG EQU CYREG_B0_UDB11_D0
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__D1_REG EQU CYREG_B0_UDB11_D1
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__F0_REG EQU CYREG_B0_UDB11_F0
ECG_ADC_Delay_Timer_TimerUDB_sT8_timerdp_u0__F1_REG EQU CYREG_B0_UDB11_F1
ECG_ADC_DSM__BUF0 EQU CYREG_DSM0_BUF0
ECG_ADC_DSM__BUF1 EQU CYREG_DSM0_BUF1
ECG_ADC_DSM__BUF2 EQU CYREG_DSM0_BUF2
ECG_ADC_DSM__BUF3 EQU CYREG_DSM0_BUF3
ECG_ADC_DSM__CLK EQU CYREG_DSM0_CLK
ECG_ADC_DSM__CR0 EQU CYREG_DSM0_CR0
ECG_ADC_DSM__CR1 EQU CYREG_DSM0_CR1
ECG_ADC_DSM__CR10 EQU CYREG_DSM0_CR10
ECG_ADC_DSM__CR11 EQU CYREG_DSM0_CR11
ECG_ADC_DSM__CR12 EQU CYREG_DSM0_CR12
ECG_ADC_DSM__CR13 EQU CYREG_DSM0_CR13
ECG_ADC_DSM__CR14 EQU CYREG_DSM0_CR14
ECG_ADC_DSM__CR15 EQU CYREG_DSM0_CR15
ECG_ADC_DSM__CR16 EQU CYREG_DSM0_CR16
ECG_ADC_DSM__CR17 EQU CYREG_DSM0_CR17
ECG_ADC_DSM__CR2 EQU CYREG_DSM0_CR2
ECG_ADC_DSM__CR3 EQU CYREG_DSM0_CR3
ECG_ADC_DSM__CR4 EQU CYREG_DSM0_CR4
ECG_ADC_DSM__CR5 EQU CYREG_DSM0_CR5
ECG_ADC_DSM__CR6 EQU CYREG_DSM0_CR6
ECG_ADC_DSM__CR7 EQU CYREG_DSM0_CR7
ECG_ADC_DSM__CR8 EQU CYREG_DSM0_CR8
ECG_ADC_DSM__CR9 EQU CYREG_DSM0_CR9
ECG_ADC_DSM__DEM0 EQU CYREG_DSM0_DEM0
ECG_ADC_DSM__DEM1 EQU CYREG_DSM0_DEM1
ECG_ADC_DSM__MISC EQU CYREG_DSM0_MISC
ECG_ADC_DSM__OUT0 EQU CYREG_DSM0_OUT0
ECG_ADC_DSM__OUT1 EQU CYREG_DSM0_OUT1
ECG_ADC_DSM__REF0 EQU CYREG_DSM0_REF0
ECG_ADC_DSM__REF1 EQU CYREG_DSM0_REF1
ECG_ADC_DSM__REF2 EQU CYREG_DSM0_REF2
ECG_ADC_DSM__REF3 EQU CYREG_DSM0_REF3
ECG_ADC_DSM__RSVD1 EQU CYREG_DSM0_RSVD1
ECG_ADC_DSM__SW0 EQU CYREG_DSM0_SW0
ECG_ADC_DSM__SW2 EQU CYREG_DSM0_SW2
ECG_ADC_DSM__SW3 EQU CYREG_DSM0_SW3
ECG_ADC_DSM__SW4 EQU CYREG_DSM0_SW4
ECG_ADC_DSM__SW6 EQU CYREG_DSM0_SW6
ECG_ADC_DSM__TR0 EQU CYREG_NPUMP_DSM_TR0
ECG_ADC_DSM__TST0 EQU CYREG_DSM0_TST0
ECG_ADC_DSM__TST1 EQU CYREG_DSM0_TST1
ECG_ADC_EOC_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
ECG_ADC_EOC_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
ECG_ADC_EOC_ISR__INTC_MASK EQU 0x02
ECG_ADC_EOC_ISR__INTC_NUMBER EQU 1
ECG_ADC_EOC_ISR__INTC_PRIOR_NUM EQU 5
ECG_ADC_EOC_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
ECG_ADC_EOC_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
ECG_ADC_EOC_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
ECG_ADC_Ext_CP_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
ECG_ADC_Ext_CP_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
ECG_ADC_Ext_CP_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
ECG_ADC_Ext_CP_Clk__CFG2_SRC_SEL_MASK EQU 0x07
ECG_ADC_Ext_CP_Clk__INDEX EQU 0x00
ECG_ADC_Ext_CP_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
ECG_ADC_Ext_CP_Clk__PM_ACT_MSK EQU 0x01
ECG_ADC_Ext_CP_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
ECG_ADC_Ext_CP_Clk__PM_STBY_MSK EQU 0x01
ECG_ADC_In__0__INTTYPE EQU CYREG_PICU4_INTTYPE0
ECG_ADC_In__0__MASK EQU 0x01
ECG_ADC_In__0__PC EQU CYREG_PRT4_PC0
ECG_ADC_In__0__PORT EQU 4
ECG_ADC_In__0__SHIFT EQU 0
ECG_ADC_In__AG EQU CYREG_PRT4_AG
ECG_ADC_In__AMUX EQU CYREG_PRT4_AMUX
ECG_ADC_In__BIE EQU CYREG_PRT4_BIE
ECG_ADC_In__BIT_MASK EQU CYREG_PRT4_BIT_MASK
ECG_ADC_In__BYP EQU CYREG_PRT4_BYP
ECG_ADC_In__CTL EQU CYREG_PRT4_CTL
ECG_ADC_In__DM0 EQU CYREG_PRT4_DM0
ECG_ADC_In__DM1 EQU CYREG_PRT4_DM1
ECG_ADC_In__DM2 EQU CYREG_PRT4_DM2
ECG_ADC_In__DR EQU CYREG_PRT4_DR
ECG_ADC_In__INP_DIS EQU CYREG_PRT4_INP_DIS
ECG_ADC_In__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU4_BASE
ECG_ADC_In__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
ECG_ADC_In__LCD_EN EQU CYREG_PRT4_LCD_EN
ECG_ADC_In__MASK EQU 0x01
ECG_ADC_In__PORT EQU 4
ECG_ADC_In__PRT EQU CYREG_PRT4_PRT
ECG_ADC_In__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
ECG_ADC_In__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
ECG_ADC_In__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
ECG_ADC_In__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
ECG_ADC_In__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
ECG_ADC_In__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
ECG_ADC_In__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
ECG_ADC_In__PS EQU CYREG_PRT4_PS
ECG_ADC_In__SHIFT EQU 0
ECG_ADC_In__SLW EQU CYREG_PRT4_SLW
ECG_ADC_IRQ__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
ECG_ADC_IRQ__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
ECG_ADC_IRQ__INTC_MASK EQU 0x20000000
ECG_ADC_IRQ__INTC_NUMBER EQU 29
ECG_ADC_IRQ__INTC_PRIOR_NUM EQU 5
ECG_ADC_IRQ__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_29
ECG_ADC_IRQ__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
ECG_ADC_IRQ__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
ECG_ADC_REF_DAC_SET_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
ECG_ADC_REF_DAC_SET_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
ECG_ADC_REF_DAC_SET_ISR__INTC_MASK EQU 0x04
ECG_ADC_REF_DAC_SET_ISR__INTC_NUMBER EQU 2
ECG_ADC_REF_DAC_SET_ISR__INTC_PRIOR_NUM EQU 5
ECG_ADC_REF_DAC_SET_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
ECG_ADC_REF_DAC_SET_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
ECG_ADC_REF_DAC_SET_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
ECG_ADC_REF_DAC_viDAC8__CR0 EQU CYREG_DAC0_CR0
ECG_ADC_REF_DAC_viDAC8__CR1 EQU CYREG_DAC0_CR1
ECG_ADC_REF_DAC_viDAC8__D EQU CYREG_DAC0_D
ECG_ADC_REF_DAC_viDAC8__PM_ACT_CFG EQU CYREG_PM_ACT_CFG8
ECG_ADC_REF_DAC_viDAC8__PM_ACT_MSK EQU 0x01
ECG_ADC_REF_DAC_viDAC8__PM_STBY_CFG EQU CYREG_PM_STBY_CFG8
ECG_ADC_REF_DAC_viDAC8__PM_STBY_MSK EQU 0x01
ECG_ADC_REF_DAC_viDAC8__STROBE EQU CYREG_DAC0_STROBE
ECG_ADC_REF_DAC_viDAC8__SW0 EQU CYREG_DAC0_SW0
ECG_ADC_REF_DAC_viDAC8__SW2 EQU CYREG_DAC0_SW2
ECG_ADC_REF_DAC_viDAC8__SW3 EQU CYREG_DAC0_SW3
ECG_ADC_REF_DAC_viDAC8__SW4 EQU CYREG_DAC0_SW4
ECG_ADC_REF_DAC_viDAC8__TR EQU CYREG_DAC0_TR
ECG_ADC_REF_DAC_viDAC8__TRIM__M1 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M1
ECG_ADC_REF_DAC_viDAC8__TRIM__M2 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M2
ECG_ADC_REF_DAC_viDAC8__TRIM__M3 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M3
ECG_ADC_REF_DAC_viDAC8__TRIM__M4 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M4
ECG_ADC_REF_DAC_viDAC8__TRIM__M5 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M5
ECG_ADC_REF_DAC_viDAC8__TRIM__M6 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M6
ECG_ADC_REF_DAC_viDAC8__TRIM__M7 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M7
ECG_ADC_REF_DAC_viDAC8__TRIM__M8 EQU CYREG_FLSHID_CUST_TABLES_DAC0_M8
ECG_ADC_REF_DAC_viDAC8__TST EQU CYREG_DAC0_TST
ECG_ADC_theACLK__CFG0 EQU CYREG_CLKDIST_ACFG0_CFG0
ECG_ADC_theACLK__CFG1 EQU CYREG_CLKDIST_ACFG0_CFG1
ECG_ADC_theACLK__CFG2 EQU CYREG_CLKDIST_ACFG0_CFG2
ECG_ADC_theACLK__CFG2_SRC_SEL_MASK EQU 0x07
ECG_ADC_theACLK__CFG3 EQU CYREG_CLKDIST_ACFG0_CFG3
ECG_ADC_theACLK__CFG3_PHASE_DLY_MASK EQU 0x0F
ECG_ADC_theACLK__INDEX EQU 0x00
ECG_ADC_theACLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG1
ECG_ADC_theACLK__PM_ACT_MSK EQU 0x01
ECG_ADC_theACLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG1
ECG_ADC_theACLK__PM_STBY_MSK EQU 0x01

/* ECG_MuxControl_N */
ECG_MuxControl_N__0__INTTYPE EQU CYREG_PICU0_INTTYPE0
ECG_MuxControl_N__0__MASK EQU 0x01
ECG_MuxControl_N__0__PC EQU CYREG_PRT0_PC0
ECG_MuxControl_N__0__PORT EQU 0
ECG_MuxControl_N__0__SHIFT EQU 0
ECG_MuxControl_N__1__INTTYPE EQU CYREG_PICU0_INTTYPE1
ECG_MuxControl_N__1__MASK EQU 0x02
ECG_MuxControl_N__1__PC EQU CYREG_PRT0_PC1
ECG_MuxControl_N__1__PORT EQU 0
ECG_MuxControl_N__1__SHIFT EQU 1
ECG_MuxControl_N__2__INTTYPE EQU CYREG_PICU0_INTTYPE2
ECG_MuxControl_N__2__MASK EQU 0x04
ECG_MuxControl_N__2__PC EQU CYREG_PRT0_PC2
ECG_MuxControl_N__2__PORT EQU 0
ECG_MuxControl_N__2__SHIFT EQU 2
ECG_MuxControl_N__AG EQU CYREG_PRT0_AG
ECG_MuxControl_N__AMUX EQU CYREG_PRT0_AMUX
ECG_MuxControl_N__BIE EQU CYREG_PRT0_BIE
ECG_MuxControl_N__BIT_MASK EQU CYREG_PRT0_BIT_MASK
ECG_MuxControl_N__BYP EQU CYREG_PRT0_BYP
ECG_MuxControl_N__CTL EQU CYREG_PRT0_CTL
ECG_MuxControl_N__DM0 EQU CYREG_PRT0_DM0
ECG_MuxControl_N__DM1 EQU CYREG_PRT0_DM1
ECG_MuxControl_N__DM2 EQU CYREG_PRT0_DM2
ECG_MuxControl_N__DR EQU CYREG_PRT0_DR
ECG_MuxControl_N__INP_DIS EQU CYREG_PRT0_INP_DIS
ECG_MuxControl_N__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE
ECG_MuxControl_N__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
ECG_MuxControl_N__LCD_EN EQU CYREG_PRT0_LCD_EN
ECG_MuxControl_N__MASK EQU 0x07
ECG_MuxControl_N__PORT EQU 0
ECG_MuxControl_N__PRT EQU CYREG_PRT0_PRT
ECG_MuxControl_N__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
ECG_MuxControl_N__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
ECG_MuxControl_N__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
ECG_MuxControl_N__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
ECG_MuxControl_N__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
ECG_MuxControl_N__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
ECG_MuxControl_N__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
ECG_MuxControl_N__PS EQU CYREG_PRT0_PS
ECG_MuxControl_N__SHIFT EQU 0
ECG_MuxControl_N__SLW EQU CYREG_PRT0_SLW

/* ECG_MuxControl_P */
ECG_MuxControl_P__0__INTTYPE EQU CYREG_PICU0_INTTYPE4
ECG_MuxControl_P__0__MASK EQU 0x10
ECG_MuxControl_P__0__PC EQU CYREG_PRT0_PC4
ECG_MuxControl_P__0__PORT EQU 0
ECG_MuxControl_P__0__SHIFT EQU 4
ECG_MuxControl_P__1__INTTYPE EQU CYREG_PICU0_INTTYPE5
ECG_MuxControl_P__1__MASK EQU 0x20
ECG_MuxControl_P__1__PC EQU CYREG_PRT0_PC5
ECG_MuxControl_P__1__PORT EQU 0
ECG_MuxControl_P__1__SHIFT EQU 5
ECG_MuxControl_P__2__INTTYPE EQU CYREG_PICU0_INTTYPE6
ECG_MuxControl_P__2__MASK EQU 0x40
ECG_MuxControl_P__2__PC EQU CYREG_PRT0_PC6
ECG_MuxControl_P__2__PORT EQU 0
ECG_MuxControl_P__2__SHIFT EQU 6
ECG_MuxControl_P__AG EQU CYREG_PRT0_AG
ECG_MuxControl_P__AMUX EQU CYREG_PRT0_AMUX
ECG_MuxControl_P__BIE EQU CYREG_PRT0_BIE
ECG_MuxControl_P__BIT_MASK EQU CYREG_PRT0_BIT_MASK
ECG_MuxControl_P__BYP EQU CYREG_PRT0_BYP
ECG_MuxControl_P__CTL EQU CYREG_PRT0_CTL
ECG_MuxControl_P__DM0 EQU CYREG_PRT0_DM0
ECG_MuxControl_P__DM1 EQU CYREG_PRT0_DM1
ECG_MuxControl_P__DM2 EQU CYREG_PRT0_DM2
ECG_MuxControl_P__DR EQU CYREG_PRT0_DR
ECG_MuxControl_P__INP_DIS EQU CYREG_PRT0_INP_DIS
ECG_MuxControl_P__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE
ECG_MuxControl_P__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
ECG_MuxControl_P__LCD_EN EQU CYREG_PRT0_LCD_EN
ECG_MuxControl_P__MASK EQU 0x70
ECG_MuxControl_P__PORT EQU 0
ECG_MuxControl_P__PRT EQU CYREG_PRT0_PRT
ECG_MuxControl_P__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
ECG_MuxControl_P__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
ECG_MuxControl_P__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
ECG_MuxControl_P__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
ECG_MuxControl_P__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
ECG_MuxControl_P__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
ECG_MuxControl_P__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
ECG_MuxControl_P__PS EQU CYREG_PRT0_PS
ECG_MuxControl_P__SHIFT EQU 4
ECG_MuxControl_P__SLW EQU CYREG_PRT0_SLW

/* ECG_Mux_N_ENB */
ECG_Mux_N_ENB__0__INTTYPE EQU CYREG_PICU0_INTTYPE3
ECG_Mux_N_ENB__0__MASK EQU 0x08
ECG_Mux_N_ENB__0__PC EQU CYREG_PRT0_PC3
ECG_Mux_N_ENB__0__PORT EQU 0
ECG_Mux_N_ENB__0__SHIFT EQU 3
ECG_Mux_N_ENB__AG EQU CYREG_PRT0_AG
ECG_Mux_N_ENB__AMUX EQU CYREG_PRT0_AMUX
ECG_Mux_N_ENB__BIE EQU CYREG_PRT0_BIE
ECG_Mux_N_ENB__BIT_MASK EQU CYREG_PRT0_BIT_MASK
ECG_Mux_N_ENB__BYP EQU CYREG_PRT0_BYP
ECG_Mux_N_ENB__CTL EQU CYREG_PRT0_CTL
ECG_Mux_N_ENB__DM0 EQU CYREG_PRT0_DM0
ECG_Mux_N_ENB__DM1 EQU CYREG_PRT0_DM1
ECG_Mux_N_ENB__DM2 EQU CYREG_PRT0_DM2
ECG_Mux_N_ENB__DR EQU CYREG_PRT0_DR
ECG_Mux_N_ENB__INP_DIS EQU CYREG_PRT0_INP_DIS
ECG_Mux_N_ENB__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE
ECG_Mux_N_ENB__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
ECG_Mux_N_ENB__LCD_EN EQU CYREG_PRT0_LCD_EN
ECG_Mux_N_ENB__MASK EQU 0x08
ECG_Mux_N_ENB__PORT EQU 0
ECG_Mux_N_ENB__PRT EQU CYREG_PRT0_PRT
ECG_Mux_N_ENB__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
ECG_Mux_N_ENB__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
ECG_Mux_N_ENB__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
ECG_Mux_N_ENB__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
ECG_Mux_N_ENB__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
ECG_Mux_N_ENB__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
ECG_Mux_N_ENB__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
ECG_Mux_N_ENB__PS EQU CYREG_PRT0_PS
ECG_Mux_N_ENB__SHIFT EQU 3
ECG_Mux_N_ENB__SLW EQU CYREG_PRT0_SLW

/* ECG_Mux_P_ENB */
ECG_Mux_P_ENB__0__INTTYPE EQU CYREG_PICU0_INTTYPE7
ECG_Mux_P_ENB__0__MASK EQU 0x80
ECG_Mux_P_ENB__0__PC EQU CYREG_PRT0_PC7
ECG_Mux_P_ENB__0__PORT EQU 0
ECG_Mux_P_ENB__0__SHIFT EQU 7
ECG_Mux_P_ENB__AG EQU CYREG_PRT0_AG
ECG_Mux_P_ENB__AMUX EQU CYREG_PRT0_AMUX
ECG_Mux_P_ENB__BIE EQU CYREG_PRT0_BIE
ECG_Mux_P_ENB__BIT_MASK EQU CYREG_PRT0_BIT_MASK
ECG_Mux_P_ENB__BYP EQU CYREG_PRT0_BYP
ECG_Mux_P_ENB__CTL EQU CYREG_PRT0_CTL
ECG_Mux_P_ENB__DM0 EQU CYREG_PRT0_DM0
ECG_Mux_P_ENB__DM1 EQU CYREG_PRT0_DM1
ECG_Mux_P_ENB__DM2 EQU CYREG_PRT0_DM2
ECG_Mux_P_ENB__DR EQU CYREG_PRT0_DR
ECG_Mux_P_ENB__INP_DIS EQU CYREG_PRT0_INP_DIS
ECG_Mux_P_ENB__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE
ECG_Mux_P_ENB__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
ECG_Mux_P_ENB__LCD_EN EQU CYREG_PRT0_LCD_EN
ECG_Mux_P_ENB__MASK EQU 0x80
ECG_Mux_P_ENB__PORT EQU 0
ECG_Mux_P_ENB__PRT EQU CYREG_PRT0_PRT
ECG_Mux_P_ENB__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
ECG_Mux_P_ENB__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
ECG_Mux_P_ENB__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
ECG_Mux_P_ENB__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
ECG_Mux_P_ENB__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
ECG_Mux_P_ENB__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
ECG_Mux_P_ENB__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
ECG_Mux_P_ENB__PS EQU CYREG_PRT0_PS
ECG_Mux_P_ENB__SHIFT EQU 7
ECG_Mux_P_ENB__SLW EQU CYREG_PRT0_SLW

/* ECG_REF_ADC_ADC_SAR */
ECG_REF_ADC_ADC_SAR__CLK EQU CYREG_SAR0_CLK
ECG_REF_ADC_ADC_SAR__CSR0 EQU CYREG_SAR0_CSR0
ECG_REF_ADC_ADC_SAR__CSR1 EQU CYREG_SAR0_CSR1
ECG_REF_ADC_ADC_SAR__CSR2 EQU CYREG_SAR0_CSR2
ECG_REF_ADC_ADC_SAR__CSR3 EQU CYREG_SAR0_CSR3
ECG_REF_ADC_ADC_SAR__CSR4 EQU CYREG_SAR0_CSR4
ECG_REF_ADC_ADC_SAR__CSR5 EQU CYREG_SAR0_CSR5
ECG_REF_ADC_ADC_SAR__CSR6 EQU CYREG_SAR0_CSR6
ECG_REF_ADC_ADC_SAR__PM_ACT_CFG EQU CYREG_PM_ACT_CFG11
ECG_REF_ADC_ADC_SAR__PM_ACT_MSK EQU 0x01
ECG_REF_ADC_ADC_SAR__PM_STBY_CFG EQU CYREG_PM_STBY_CFG11
ECG_REF_ADC_ADC_SAR__PM_STBY_MSK EQU 0x01
ECG_REF_ADC_ADC_SAR__SW0 EQU CYREG_SAR0_SW0
ECG_REF_ADC_ADC_SAR__SW2 EQU CYREG_SAR0_SW2
ECG_REF_ADC_ADC_SAR__SW3 EQU CYREG_SAR0_SW3
ECG_REF_ADC_ADC_SAR__SW4 EQU CYREG_SAR0_SW4
ECG_REF_ADC_ADC_SAR__SW6 EQU CYREG_SAR0_SW6
ECG_REF_ADC_ADC_SAR__TR0 EQU CYREG_SAR0_TR0
ECG_REF_ADC_ADC_SAR__WRK0 EQU CYREG_SAR0_WRK0
ECG_REF_ADC_ADC_SAR__WRK1 EQU CYREG_SAR0_WRK1

/* ECG_REF_ADC_EOC_ISR */
ECG_REF_ADC_EOC_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
ECG_REF_ADC_EOC_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
ECG_REF_ADC_EOC_ISR__INTC_MASK EQU 0x08
ECG_REF_ADC_EOC_ISR__INTC_NUMBER EQU 3
ECG_REF_ADC_EOC_ISR__INTC_PRIOR_NUM EQU 5
ECG_REF_ADC_EOC_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
ECG_REF_ADC_EOC_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
ECG_REF_ADC_EOC_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

/* ECG_REF_ADC_IRQ */
ECG_REF_ADC_IRQ__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
ECG_REF_ADC_IRQ__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
ECG_REF_ADC_IRQ__INTC_MASK EQU 0x10
ECG_REF_ADC_IRQ__INTC_NUMBER EQU 4
ECG_REF_ADC_IRQ__INTC_PRIOR_NUM EQU 5
ECG_REF_ADC_IRQ__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
ECG_REF_ADC_IRQ__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
ECG_REF_ADC_IRQ__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

/* ECG_REF_ADC_theACLK */
ECG_REF_ADC_theACLK__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
ECG_REF_ADC_theACLK__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
ECG_REF_ADC_theACLK__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
ECG_REF_ADC_theACLK__CFG2_SRC_SEL_MASK EQU 0x07
ECG_REF_ADC_theACLK__INDEX EQU 0x02
ECG_REF_ADC_theACLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
ECG_REF_ADC_theACLK__PM_ACT_MSK EQU 0x04
ECG_REF_ADC_theACLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
ECG_REF_ADC_theACLK__PM_STBY_MSK EQU 0x04

/* ECG_REF_DRIVE */
ECG_REF_DRIVE__0__INTTYPE EQU CYREG_PICU3_INTTYPE6
ECG_REF_DRIVE__0__MASK EQU 0x40
ECG_REF_DRIVE__0__PC EQU CYREG_PRT3_PC6
ECG_REF_DRIVE__0__PORT EQU 3
ECG_REF_DRIVE__0__SHIFT EQU 6
ECG_REF_DRIVE__AG EQU CYREG_PRT3_AG
ECG_REF_DRIVE__AMUX EQU CYREG_PRT3_AMUX
ECG_REF_DRIVE__BIE EQU CYREG_PRT3_BIE
ECG_REF_DRIVE__BIT_MASK EQU CYREG_PRT3_BIT_MASK
ECG_REF_DRIVE__BYP EQU CYREG_PRT3_BYP
ECG_REF_DRIVE__CTL EQU CYREG_PRT3_CTL
ECG_REF_DRIVE__DM0 EQU CYREG_PRT3_DM0
ECG_REF_DRIVE__DM1 EQU CYREG_PRT3_DM1
ECG_REF_DRIVE__DM2 EQU CYREG_PRT3_DM2
ECG_REF_DRIVE__DR EQU CYREG_PRT3_DR
ECG_REF_DRIVE__INP_DIS EQU CYREG_PRT3_INP_DIS
ECG_REF_DRIVE__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
ECG_REF_DRIVE__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
ECG_REF_DRIVE__LCD_EN EQU CYREG_PRT3_LCD_EN
ECG_REF_DRIVE__MASK EQU 0x40
ECG_REF_DRIVE__PORT EQU 3
ECG_REF_DRIVE__PRT EQU CYREG_PRT3_PRT
ECG_REF_DRIVE__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
ECG_REF_DRIVE__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
ECG_REF_DRIVE__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
ECG_REF_DRIVE__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
ECG_REF_DRIVE__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
ECG_REF_DRIVE__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
ECG_REF_DRIVE__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
ECG_REF_DRIVE__PS EQU CYREG_PRT3_PS
ECG_REF_DRIVE__SHIFT EQU 6
ECG_REF_DRIVE__SLW EQU CYREG_PRT3_SLW
ECG_REF_DRIVE_DAC_viDAC8__CR0 EQU CYREG_DAC1_CR0
ECG_REF_DRIVE_DAC_viDAC8__CR1 EQU CYREG_DAC1_CR1
ECG_REF_DRIVE_DAC_viDAC8__D EQU CYREG_DAC1_D
ECG_REF_DRIVE_DAC_viDAC8__PM_ACT_CFG EQU CYREG_PM_ACT_CFG8
ECG_REF_DRIVE_DAC_viDAC8__PM_ACT_MSK EQU 0x02
ECG_REF_DRIVE_DAC_viDAC8__PM_STBY_CFG EQU CYREG_PM_STBY_CFG8
ECG_REF_DRIVE_DAC_viDAC8__PM_STBY_MSK EQU 0x02
ECG_REF_DRIVE_DAC_viDAC8__STROBE EQU CYREG_DAC1_STROBE
ECG_REF_DRIVE_DAC_viDAC8__SW0 EQU CYREG_DAC1_SW0
ECG_REF_DRIVE_DAC_viDAC8__SW2 EQU CYREG_DAC1_SW2
ECG_REF_DRIVE_DAC_viDAC8__SW3 EQU CYREG_DAC1_SW3
ECG_REF_DRIVE_DAC_viDAC8__SW4 EQU CYREG_DAC1_SW4
ECG_REF_DRIVE_DAC_viDAC8__TR EQU CYREG_DAC1_TR
ECG_REF_DRIVE_DAC_viDAC8__TRIM__M1 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M1
ECG_REF_DRIVE_DAC_viDAC8__TRIM__M2 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M2
ECG_REF_DRIVE_DAC_viDAC8__TRIM__M3 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M3
ECG_REF_DRIVE_DAC_viDAC8__TRIM__M4 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M4
ECG_REF_DRIVE_DAC_viDAC8__TRIM__M5 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M5
ECG_REF_DRIVE_DAC_viDAC8__TRIM__M6 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M6
ECG_REF_DRIVE_DAC_viDAC8__TRIM__M7 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M7
ECG_REF_DRIVE_DAC_viDAC8__TRIM__M8 EQU CYREG_FLSHID_CUST_TABLES_DAC1_M8
ECG_REF_DRIVE_DAC_viDAC8__TST EQU CYREG_DAC1_TST

/* ECG_RL_DRIVE */
ECG_RL_DRIVE__0__INTTYPE EQU CYREG_PICU3_INTTYPE7
ECG_RL_DRIVE__0__MASK EQU 0x80
ECG_RL_DRIVE__0__PC EQU CYREG_PRT3_PC7
ECG_RL_DRIVE__0__PORT EQU 3
ECG_RL_DRIVE__0__SHIFT EQU 7
ECG_RL_DRIVE__AG EQU CYREG_PRT3_AG
ECG_RL_DRIVE__AMUX EQU CYREG_PRT3_AMUX
ECG_RL_DRIVE__BIE EQU CYREG_PRT3_BIE
ECG_RL_DRIVE__BIT_MASK EQU CYREG_PRT3_BIT_MASK
ECG_RL_DRIVE__BYP EQU CYREG_PRT3_BYP
ECG_RL_DRIVE__CTL EQU CYREG_PRT3_CTL
ECG_RL_DRIVE__DM0 EQU CYREG_PRT3_DM0
ECG_RL_DRIVE__DM1 EQU CYREG_PRT3_DM1
ECG_RL_DRIVE__DM2 EQU CYREG_PRT3_DM2
ECG_RL_DRIVE__DR EQU CYREG_PRT3_DR
ECG_RL_DRIVE__INP_DIS EQU CYREG_PRT3_INP_DIS
ECG_RL_DRIVE__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
ECG_RL_DRIVE__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
ECG_RL_DRIVE__LCD_EN EQU CYREG_PRT3_LCD_EN
ECG_RL_DRIVE__MASK EQU 0x80
ECG_RL_DRIVE__PORT EQU 3
ECG_RL_DRIVE__PRT EQU CYREG_PRT3_PRT
ECG_RL_DRIVE__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
ECG_RL_DRIVE__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
ECG_RL_DRIVE__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
ECG_RL_DRIVE__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
ECG_RL_DRIVE__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
ECG_RL_DRIVE__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
ECG_RL_DRIVE__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
ECG_RL_DRIVE__PS EQU CYREG_PRT3_PS
ECG_RL_DRIVE__SHIFT EQU 7
ECG_RL_DRIVE__SLW EQU CYREG_PRT3_SLW
ECG_RL_DRIVE_DAC_viDAC8__CR0 EQU CYREG_DAC3_CR0
ECG_RL_DRIVE_DAC_viDAC8__CR1 EQU CYREG_DAC3_CR1
ECG_RL_DRIVE_DAC_viDAC8__D EQU CYREG_DAC3_D
ECG_RL_DRIVE_DAC_viDAC8__PM_ACT_CFG EQU CYREG_PM_ACT_CFG8
ECG_RL_DRIVE_DAC_viDAC8__PM_ACT_MSK EQU 0x08
ECG_RL_DRIVE_DAC_viDAC8__PM_STBY_CFG EQU CYREG_PM_STBY_CFG8
ECG_RL_DRIVE_DAC_viDAC8__PM_STBY_MSK EQU 0x08
ECG_RL_DRIVE_DAC_viDAC8__STROBE EQU CYREG_DAC3_STROBE
ECG_RL_DRIVE_DAC_viDAC8__SW0 EQU CYREG_DAC3_SW0
ECG_RL_DRIVE_DAC_viDAC8__SW2 EQU CYREG_DAC3_SW2
ECG_RL_DRIVE_DAC_viDAC8__SW3 EQU CYREG_DAC3_SW3
ECG_RL_DRIVE_DAC_viDAC8__SW4 EQU CYREG_DAC3_SW4
ECG_RL_DRIVE_DAC_viDAC8__TR EQU CYREG_DAC3_TR
ECG_RL_DRIVE_DAC_viDAC8__TRIM__M1 EQU CYREG_FLSHID_CUST_TABLES_DAC3_M1
ECG_RL_DRIVE_DAC_viDAC8__TRIM__M2 EQU CYREG_FLSHID_CUST_TABLES_DAC3_M2
ECG_RL_DRIVE_DAC_viDAC8__TRIM__M3 EQU CYREG_FLSHID_CUST_TABLES_DAC3_M3
ECG_RL_DRIVE_DAC_viDAC8__TRIM__M4 EQU CYREG_FLSHID_CUST_TABLES_DAC3_M4
ECG_RL_DRIVE_DAC_viDAC8__TRIM__M5 EQU CYREG_FLSHID_CUST_TABLES_DAC3_M5
ECG_RL_DRIVE_DAC_viDAC8__TRIM__M6 EQU CYREG_FLSHID_CUST_TABLES_DAC3_M6
ECG_RL_DRIVE_DAC_viDAC8__TRIM__M7 EQU CYREG_FLSHID_CUST_TABLES_DAC3_M7
ECG_RL_DRIVE_DAC_viDAC8__TRIM__M8 EQU CYREG_FLSHID_CUST_TABLES_DAC3_M8
ECG_RL_DRIVE_DAC_viDAC8__TST EQU CYREG_DAC3_TST

/* LED0 */
LED0__0__INTTYPE EQU CYREG_PICU2_INTTYPE0
LED0__0__MASK EQU 0x01
LED0__0__PC EQU CYREG_PRT2_PC0
LED0__0__PORT EQU 2
LED0__0__SHIFT EQU 0
LED0__AG EQU CYREG_PRT2_AG
LED0__AMUX EQU CYREG_PRT2_AMUX
LED0__BIE EQU CYREG_PRT2_BIE
LED0__BIT_MASK EQU CYREG_PRT2_BIT_MASK
LED0__BYP EQU CYREG_PRT2_BYP
LED0__CTL EQU CYREG_PRT2_CTL
LED0__DM0 EQU CYREG_PRT2_DM0
LED0__DM1 EQU CYREG_PRT2_DM1
LED0__DM2 EQU CYREG_PRT2_DM2
LED0__DR EQU CYREG_PRT2_DR
LED0__INP_DIS EQU CYREG_PRT2_INP_DIS
LED0__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU2_BASE
LED0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
LED0__LCD_EN EQU CYREG_PRT2_LCD_EN
LED0__MASK EQU 0x01
LED0__PORT EQU 2
LED0__PRT EQU CYREG_PRT2_PRT
LED0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
LED0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
LED0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
LED0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
LED0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
LED0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
LED0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
LED0__PS EQU CYREG_PRT2_PS
LED0__SHIFT EQU 0
LED0__SLW EQU CYREG_PRT2_SLW

/* LED1 */
LED1__0__INTTYPE EQU CYREG_PICU2_INTTYPE1
LED1__0__MASK EQU 0x02
LED1__0__PC EQU CYREG_PRT2_PC1
LED1__0__PORT EQU 2
LED1__0__SHIFT EQU 1
LED1__AG EQU CYREG_PRT2_AG
LED1__AMUX EQU CYREG_PRT2_AMUX
LED1__BIE EQU CYREG_PRT2_BIE
LED1__BIT_MASK EQU CYREG_PRT2_BIT_MASK
LED1__BYP EQU CYREG_PRT2_BYP
LED1__CTL EQU CYREG_PRT2_CTL
LED1__DM0 EQU CYREG_PRT2_DM0
LED1__DM1 EQU CYREG_PRT2_DM1
LED1__DM2 EQU CYREG_PRT2_DM2
LED1__DR EQU CYREG_PRT2_DR
LED1__INP_DIS EQU CYREG_PRT2_INP_DIS
LED1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU2_BASE
LED1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
LED1__LCD_EN EQU CYREG_PRT2_LCD_EN
LED1__MASK EQU 0x02
LED1__PORT EQU 2
LED1__PRT EQU CYREG_PRT2_PRT
LED1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
LED1__PS EQU CYREG_PRT2_PS
LED1__SHIFT EQU 1
LED1__SLW EQU CYREG_PRT2_SLW

/* PB1 */
PB1__0__INTTYPE EQU CYREG_PICU2_INTTYPE2
PB1__0__MASK EQU 0x04
PB1__0__PC EQU CYREG_PRT2_PC2
PB1__0__PORT EQU 2
PB1__0__SHIFT EQU 2
PB1__AG EQU CYREG_PRT2_AG
PB1__AMUX EQU CYREG_PRT2_AMUX
PB1__BIE EQU CYREG_PRT2_BIE
PB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK
PB1__BYP EQU CYREG_PRT2_BYP
PB1__CTL EQU CYREG_PRT2_CTL
PB1__DM0 EQU CYREG_PRT2_DM0
PB1__DM1 EQU CYREG_PRT2_DM1
PB1__DM2 EQU CYREG_PRT2_DM2
PB1__DR EQU CYREG_PRT2_DR
PB1__INP_DIS EQU CYREG_PRT2_INP_DIS
PB1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU2_BASE
PB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
PB1__LCD_EN EQU CYREG_PRT2_LCD_EN
PB1__MASK EQU 0x04
PB1__PORT EQU 2
PB1__PRT EQU CYREG_PRT2_PRT
PB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
PB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
PB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
PB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
PB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
PB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
PB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
PB1__PS EQU CYREG_PRT2_PS
PB1__SHIFT EQU 2
PB1__SLW EQU CYREG_PRT2_SLW

/* Sample_Clock */
Sample_Clock__CFG0 EQU CYREG_CLKDIST_DCFG4_CFG0
Sample_Clock__CFG1 EQU CYREG_CLKDIST_DCFG4_CFG1
Sample_Clock__CFG2 EQU CYREG_CLKDIST_DCFG4_CFG2
Sample_Clock__CFG2_SRC_SEL_MASK EQU 0x07
Sample_Clock__INDEX EQU 0x04
Sample_Clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
Sample_Clock__PM_ACT_MSK EQU 0x10
Sample_Clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
Sample_Clock__PM_STBY_MSK EQU 0x10

/* Timer_Clock */
Timer_Clock__CFG0 EQU CYREG_CLKDIST_DCFG3_CFG0
Timer_Clock__CFG1 EQU CYREG_CLKDIST_DCFG3_CFG1
Timer_Clock__CFG2 EQU CYREG_CLKDIST_DCFG3_CFG2
Timer_Clock__CFG2_SRC_SEL_MASK EQU 0x07
Timer_Clock__INDEX EQU 0x03
Timer_Clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
Timer_Clock__PM_ACT_MSK EQU 0x08
Timer_Clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
Timer_Clock__PM_STBY_MSK EQU 0x08

/* USBUART */
USBUART_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBUART_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBUART_arb_int__INTC_MASK EQU 0x400000
USBUART_arb_int__INTC_NUMBER EQU 22
USBUART_arb_int__INTC_PRIOR_NUM EQU 6
USBUART_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
USBUART_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBUART_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBUART_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBUART_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBUART_bus_reset__INTC_MASK EQU 0x800000
USBUART_bus_reset__INTC_NUMBER EQU 23
USBUART_bus_reset__INTC_PRIOR_NUM EQU 6
USBUART_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
USBUART_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBUART_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBUART_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7
USBUART_Dm__0__MASK EQU 0x80
USBUART_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
USBUART_Dm__0__PORT EQU 15
USBUART_Dm__0__SHIFT EQU 7
USBUART_Dm__AG EQU CYREG_PRT15_AG
USBUART_Dm__AMUX EQU CYREG_PRT15_AMUX
USBUART_Dm__BIE EQU CYREG_PRT15_BIE
USBUART_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
USBUART_Dm__BYP EQU CYREG_PRT15_BYP
USBUART_Dm__CTL EQU CYREG_PRT15_CTL
USBUART_Dm__DM0 EQU CYREG_PRT15_DM0
USBUART_Dm__DM1 EQU CYREG_PRT15_DM1
USBUART_Dm__DM2 EQU CYREG_PRT15_DM2
USBUART_Dm__DR EQU CYREG_PRT15_DR
USBUART_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
USBUART_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
USBUART_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
USBUART_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
USBUART_Dm__MASK EQU 0x80
USBUART_Dm__PORT EQU 15
USBUART_Dm__PRT EQU CYREG_PRT15_PRT
USBUART_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
USBUART_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
USBUART_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
USBUART_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
USBUART_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
USBUART_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
USBUART_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
USBUART_Dm__PS EQU CYREG_PRT15_PS
USBUART_Dm__SHIFT EQU 7
USBUART_Dm__SLW EQU CYREG_PRT15_SLW
USBUART_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6
USBUART_Dp__0__MASK EQU 0x40
USBUART_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
USBUART_Dp__0__PORT EQU 15
USBUART_Dp__0__SHIFT EQU 6
USBUART_Dp__AG EQU CYREG_PRT15_AG
USBUART_Dp__AMUX EQU CYREG_PRT15_AMUX
USBUART_Dp__BIE EQU CYREG_PRT15_BIE
USBUART_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
USBUART_Dp__BYP EQU CYREG_PRT15_BYP
USBUART_Dp__CTL EQU CYREG_PRT15_CTL
USBUART_Dp__DM0 EQU CYREG_PRT15_DM0
USBUART_Dp__DM1 EQU CYREG_PRT15_DM1
USBUART_Dp__DM2 EQU CYREG_PRT15_DM2
USBUART_Dp__DR EQU CYREG_PRT15_DR
USBUART_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
USBUART_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
USBUART_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
USBUART_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
USBUART_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
USBUART_Dp__MASK EQU 0x40
USBUART_Dp__PORT EQU 15
USBUART_Dp__PRT EQU CYREG_PRT15_PRT
USBUART_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
USBUART_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
USBUART_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
USBUART_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
USBUART_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
USBUART_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
USBUART_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
USBUART_Dp__PS EQU CYREG_PRT15_PS
USBUART_Dp__SHIFT EQU 6
USBUART_Dp__SLW EQU CYREG_PRT15_SLW
USBUART_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
USBUART_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBUART_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBUART_dp_int__INTC_MASK EQU 0x1000
USBUART_dp_int__INTC_NUMBER EQU 12
USBUART_dp_int__INTC_PRIOR_NUM EQU 6
USBUART_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
USBUART_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBUART_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBUART_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBUART_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBUART_ep_0__INTC_MASK EQU 0x1000000
USBUART_ep_0__INTC_NUMBER EQU 24
USBUART_ep_0__INTC_PRIOR_NUM EQU 6
USBUART_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
USBUART_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBUART_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBUART_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBUART_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBUART_ep_1__INTC_MASK EQU 0x20
USBUART_ep_1__INTC_NUMBER EQU 5
USBUART_ep_1__INTC_PRIOR_NUM EQU 6
USBUART_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
USBUART_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBUART_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBUART_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBUART_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBUART_ep_2__INTC_MASK EQU 0x40
USBUART_ep_2__INTC_NUMBER EQU 6
USBUART_ep_2__INTC_PRIOR_NUM EQU 6
USBUART_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
USBUART_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBUART_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBUART_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBUART_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBUART_ep_3__INTC_MASK EQU 0x80
USBUART_ep_3__INTC_NUMBER EQU 7
USBUART_ep_3__INTC_PRIOR_NUM EQU 7
USBUART_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
USBUART_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBUART_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBUART_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
USBUART_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
USBUART_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
USBUART_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
USBUART_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
USBUART_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
USBUART_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
USBUART_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
USBUART_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
USBUART_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
USBUART_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
USBUART_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
USBUART_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
USBUART_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
USBUART_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
USBUART_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
USBUART_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
USBUART_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
USBUART_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
USBUART_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
USBUART_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
USBUART_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
USBUART_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
USBUART_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
USBUART_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
USBUART_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
USBUART_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
USBUART_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
USBUART_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
USBUART_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
USBUART_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
USBUART_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
USBUART_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
USBUART_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
USBUART_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
USBUART_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
USBUART_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
USBUART_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
USBUART_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
USBUART_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
USBUART_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
USBUART_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
USBUART_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
USBUART_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
USBUART_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
USBUART_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
USBUART_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
USBUART_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
USBUART_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
USBUART_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
USBUART_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
USBUART_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
USBUART_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
USBUART_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
USBUART_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
USBUART_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
USBUART_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
USBUART_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
USBUART_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
USBUART_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
USBUART_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
USBUART_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
USBUART_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
USBUART_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
USBUART_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
USBUART_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
USBUART_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
USBUART_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
USBUART_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
USBUART_USB__CR0 EQU CYREG_USB_CR0
USBUART_USB__CR1 EQU CYREG_USB_CR1
USBUART_USB__CWA EQU CYREG_USB_CWA
USBUART_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
USBUART_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
USBUART_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
USBUART_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
USBUART_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
USBUART_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
USBUART_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
USBUART_USB__EP0_CR EQU CYREG_USB_EP0_CR
USBUART_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
USBUART_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
USBUART_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
USBUART_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
USBUART_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
USBUART_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
USBUART_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
USBUART_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
USBUART_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
USBUART_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
USBUART_USB__PM_ACT_MSK EQU 0x01
USBUART_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
USBUART_USB__PM_STBY_MSK EQU 0x01
USBUART_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
USBUART_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
USBUART_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
USBUART_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
USBUART_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
USBUART_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
USBUART_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
USBUART_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
USBUART_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
USBUART_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
USBUART_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
USBUART_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
USBUART_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
USBUART_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
USBUART_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
USBUART_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
USBUART_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
USBUART_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
USBUART_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
USBUART_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
USBUART_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
USBUART_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
USBUART_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
USBUART_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
USBUART_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
USBUART_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
USBUART_USB__SOF0 EQU CYREG_USB_SOF0
USBUART_USB__SOF1 EQU CYREG_USB_SOF1
USBUART_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
USBUART_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
USBUART_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1

/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 80000000
BCLK__BUS_CLK__KHZ EQU 80000
BCLK__BUS_CLK__MHZ EQU 80
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PSOC4A EQU 16
CYDEV_CHIP_DIE_PSOC5LP EQU 2
CYDEV_CHIP_DIE_PSOC5TM EQU 3
CYDEV_CHIP_DIE_TMA4 EQU 4
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_FM0P EQU 5
CYDEV_CHIP_FAMILY_FM3 EQU 6
CYDEV_CHIP_FAMILY_FM4 EQU 7
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_PSOC6 EQU 4
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x2E160069
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 16
CYDEV_CHIP_MEMBER_4D EQU 12
CYDEV_CHIP_MEMBER_4E EQU 6
CYDEV_CHIP_MEMBER_4F EQU 17
CYDEV_CHIP_MEMBER_4G EQU 4
CYDEV_CHIP_MEMBER_4H EQU 15
CYDEV_CHIP_MEMBER_4I EQU 21
CYDEV_CHIP_MEMBER_4J EQU 13
CYDEV_CHIP_MEMBER_4K EQU 14
CYDEV_CHIP_MEMBER_4L EQU 20
CYDEV_CHIP_MEMBER_4M EQU 19
CYDEV_CHIP_MEMBER_4N EQU 9
CYDEV_CHIP_MEMBER_4O EQU 7
CYDEV_CHIP_MEMBER_4P EQU 18
CYDEV_CHIP_MEMBER_4Q EQU 11
CYDEV_CHIP_MEMBER_4R EQU 8
CYDEV_CHIP_MEMBER_4S EQU 10
CYDEV_CHIP_MEMBER_4U EQU 5
CYDEV_CHIP_MEMBER_5A EQU 3
CYDEV_CHIP_MEMBER_5B EQU 2
CYDEV_CHIP_MEMBER_6A EQU 22
CYDEV_CHIP_MEMBER_FM3 EQU 26
CYDEV_CHIP_MEMBER_FM4 EQU 27
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1
CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1
CYDEV_CHIP_REV_TMA4_ES EQU 17
CYDEV_CHIP_REV_TMA4_ES2 EQU 33
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
CYDEV_CHIP_REVISION_4G_ES EQU 17
CYDEV_CHIP_REVISION_4G_ES2 EQU 33
CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0
CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_DMA EQU 0
CYDEV_CONFIGURATION_ECC EQU 1
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_DEBUG_ENABLE_MASK EQU 0x20
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DEBUGGING_XRES EQU 0
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x80
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
CYDEV_INTR_RISING EQU 0x0000001F
CYDEV_IS_EXPORTING_CODE EQU 0
CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 2
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0
CYDEV_STACK_SIZE EQU 0x0800
CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 0
CYDEV_VDDA_MV EQU 5000
CYDEV_VDDD_MV EQU 5000
CYDEV_VDDIO0_MV EQU 5000
CYDEV_VDDIO1_MV EQU 5000
CYDEV_VDDIO2_MV EQU 5000
CYDEV_VDDIO3_MV EQU 5000
CYDEV_VIO0_MV EQU 5000
CYDEV_VIO1_MV EQU 5000
CYDEV_VIO2_MV EQU 5000
CYDEV_VIO3_MV EQU 5000
CYIPBLOCK_ARM_CM3_VERSION EQU 0
CYIPBLOCK_P3_ANAIF_VERSION EQU 0
CYIPBLOCK_P3_CAN_VERSION EQU 0
CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
CYIPBLOCK_P3_COMP_VERSION EQU 0
CYIPBLOCK_P3_DECIMATOR_VERSION EQU 0
CYIPBLOCK_P3_DFB_VERSION EQU 0
CYIPBLOCK_P3_DMA_VERSION EQU 0
CYIPBLOCK_P3_DRQ_VERSION EQU 0
CYIPBLOCK_P3_DSM_VERSION EQU 0
CYIPBLOCK_P3_EMIF_VERSION EQU 0
CYIPBLOCK_P3_I2C_VERSION EQU 0
CYIPBLOCK_P3_LCD_VERSION EQU 0
CYIPBLOCK_P3_LPF_VERSION EQU 0
CYIPBLOCK_P3_OPAMP_VERSION EQU 0
CYIPBLOCK_P3_PM_VERSION EQU 0
CYIPBLOCK_P3_SCCT_VERSION EQU 0
CYIPBLOCK_P3_TIMER_VERSION EQU 0
CYIPBLOCK_P3_USB_VERSION EQU 0
CYIPBLOCK_P3_VIDAC_VERSION EQU 0
CYIPBLOCK_P3_VREF_VERSION EQU 0
CYIPBLOCK_S8_GPIO_VERSION EQU 0
CYIPBLOCK_S8_IRQ_VERSION EQU 0
CYIPBLOCK_S8_SAR_VERSION EQU 0
CYIPBLOCK_S8_SIO_VERSION EQU 0
CYIPBLOCK_S8_UDB_VERSION EQU 0
DMA_CHANNELS_USED__MASK0 EQU 0x00000400
CYDEV_BOOTLOADER_ENABLE EQU 0

#endif /* INCLUDED_CYFITTERIAR_INC */
